The present invention relates to a semiconductor memory device, and more particularly, to a technology of enhancing characteristics of a clock through an improved distribution of the clocks of the memory device.
FIG. 1 shows a clock distribution network of a conventional ultra-high speed semiconductor memory device.
Shown in FIG. 1 is a clock supply portion 110 for supplying a clock provided from outside of a chip to the inside of a memory device. The clock supply portion 110 includes among its elements a buffer for receiving a clock from the outside, a phase locked loop (PLL) for generating a clean clock when high jitter exists in the clock, and a duty cycle correction (DCC) circuit for correcting the clock when there is a mismatch between its duty cycles.
Also shown in the drawing is a clock transfer portion 120 for transferring the clock from the clock supply portion 110 to each of elements in the memory device. The clock transfer portion 120 is composed of plural repeaters 121 to 126 arranged at the center of lines conveying the clock for repeating the clock.
Data input/output portions 131 to 146 for inputting/outputting data in accordance with the clock are provided through the data transfer portion 120. In an ultra-high speed memory such as a GDDR5, data is inputted/outputted in synchronism with the clock (more correctly, the WCK clock signal as defined in the JEDEC specification for GDDR5), without using a separate data strobe signal DQS. Here, the data strobe signal DQS is a clock serving as a reference for timing of data transfer between a chipset and a semiconductor memory device.
FIG. 2 is a diagram showing one of the existing repeaters 121 to 126 for transferring signals at a CMOS level.
As shown in the drawing, the existing repeater is provided with a NAND gate 201 and inverters 202, 203, and 204 for accepting an enable signal EN and a clock CLKIN.
The existing repeater conveys the clock CLKIN to its own output terminal only when the enable signal EN is enabled to a logic ‘high’ level. It does not convey the clock to its own output terminal when the enable signal EN is disabled to a logic ‘low’ level. That is, when the enable signal EN is disabled, the output terminal of the existing repeater is fixed to a logic ‘low’ level.
Also shown in FIG. 2 is the configuration of one of the inverters of the repeater. As is well-known in the art, an inverter may include a PMOS transistor and an NMOS transistor coupled in series. When a ‘high’ signal is inputted, the NMOS transistor is turned on to output to its output terminal a ‘low’ signal having a VSS level. On the other hand, when a ‘low’ signal is inputted, the PMOS transistor is turned on to output a ‘high’ signal having a VDD level.
The level of a signal used to drive the inverter in this way, with the ‘high’ signal having a VDD level and the ‘low’ signal having a VSS level, is called a CMOS level. In the following description, a circuit conveying a signal at a CMOS level is also referred to as a CMOS circuit.
The clock supply portion 110 and the clock transfer portion 120 in the existing semiconductor memory device are each composed of a CMOS circuit. However, such a CMOS circuit has poor noise rejection characteristics. Thus, jitter components occur in a clock signal due to power noise generated within the memory device. That is, since the existing memory device uses a CMOS circuit with poor noise immunity for clock distribution, this results in increased jitter components in the clock signal. This gives rise to a reduction in stability when the memory device operates at a high speed.